36 lines
874 B
Plaintext
36 lines
874 B
Plaintext
`include "first_counter.v"
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module first_counter_tb();
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// Declare inputs as regs and outputs as wires
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reg clock, reset, enable;
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wire [3:0] counter_out;
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// Initialize all variables
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initial begin
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$display ("time\t clk reset enable counter");
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$monitor ("%g\t %b %b %b %b",
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$time, clock, reset, enable, counter_out);
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clock = 1; // initial value of clock
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reset = 0; // initial value of reset
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enable = 0; // initial value of enable
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#5 reset = 1; // Assert the reset
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#10 reset = 0; // De-assert the reset
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#10 enable = 1; // Assert enable
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#100 enable = 0; // De-assert enable
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#5 $finish; // Terminate simulation
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end
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// Clock generator
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always begin
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#5 clock = ~clock; // Toggle clock every 5 ticks
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end
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// Connect DUT to test bench
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first_counter U_counter (
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clock,
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reset,
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enable,
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counter_out
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);
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endmodule
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