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deps: V8: cherry-pick 6ea594ff7132 

Original commit message:

    [riscv] Skip check sv57 when enable pointer compress

    Change-Id: I4332d3849d113af105630c0e20cd2b5e3deb9392
    Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/5430889
    Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
    Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
    Cr-Commit-Position: refs/heads/main@{#93244}

Refs: 6ea594ff71
PR-URL: https://github.com/nodejs/node/pull/53412
Reviewed-By: Jiawen Geng <technicalcute@gmail.com>
Reviewed-By: Michaël Zasso <targos@protonmail.com>
Reviewed-By: Richard Lau <rlau@redhat.com>
Reviewed-By: Marco Ippolito <marcoippolito54@gmail.com>
Reviewed-By: Rafael Gonzaga <rafael.nunu@hotmail.com>
Reviewed-By: Luigi Pinca <luigipinca@gmail.com>
pull/53592/head
kxxt 2024-06-10 11:38:52 +08:00 committed by Michaël Zasso
parent f9075ff38e
commit 2defaaf771
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2 changed files with 18 additions and 20 deletions
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2
common.gypi
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@ -36,7 +36,7 @@
# Reset this number to 0 on major V8 upgrades.
# Increment by one for each non-official patch applied to deps/v8.
'v8_embedder_string': '-node.13',
'v8_embedder_string': '-node.14',
##### V8 defaults for Node.js #####

36
deps/v8/src/codegen/riscv/assembler-riscv.cc vendored
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@ -83,10 +83,12 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
base::CPU cpu;
if (cpu.has_fpu()) supported_ |= 1u << FPU;
if (cpu.has_rvv()) supported_ |= 1u << RISCV_SIMD;
#ifdef V8_COMPRESS_POINTERS
if (cpu.riscv_mmu() == base::CPU::RV_MMU_MODE::kRiscvSV57) {
FATAL("SV57 is not supported");
UNIMPLEMENTED();
}
#endif
// Set a static value on whether SIMD is supported.
// This variable is only used for certain archs to query SupportWasmSimd128()
// at runtime in builtins using an extern ref. Other callers should use
@ -1086,25 +1088,21 @@ void Assembler::GeneralLi(Register rd, int64_t imm) {
void Assembler::li_ptr(Register rd, int64_t imm) {
base::CPU cpu;
if (cpu.riscv_mmu() != base::CPU::RV_MMU_MODE::kRiscvSV57) {
// Initialize rd with an address
// Pointers are 48 bits
// 6 fixed instructions are generated
DCHECK_EQ((imm & 0xfff0000000000000ll), 0);
int64_t a6 = imm & 0x3f; // bits 0:5. 6 bits
int64_t b11 = (imm >> 6) & 0x7ff; // bits 6:11. 11 bits
int64_t high_31 = (imm >> 17) & 0x7fffffff; // 31 bits
int64_t high_20 = ((high_31 + 0x800) >> 12); // 19 bits
int64_t low_12 = high_31 & 0xfff; // 12 bits
lui(rd, (int32_t)high_20);
addi(rd, rd, low_12); // 31 bits in rd.
slli(rd, rd, 11); // Space for next 11 bis
ori(rd, rd, b11); // 11 bits are put in. 42 bit in rd
slli(rd, rd, 6); // Space for next 6 bits
ori(rd, rd, a6); // 6 bits are put in. 48 bis in rd
} else {
FATAL("SV57 is not supported");
}
// Initialize rd with an address
// Pointers are 48 bits
// 6 fixed instructions are generated
DCHECK_EQ((imm & 0xfff0000000000000ll), 0);
int64_t a6 = imm & 0x3f; // bits 0:5. 6 bits
int64_t b11 = (imm >> 6) & 0x7ff; // bits 6:11. 11 bits
int64_t high_31 = (imm >> 17) & 0x7fffffff; // 31 bits
int64_t high_20 = ((high_31 + 0x800) >> 12); // 19 bits
int64_t low_12 = high_31 & 0xfff; // 12 bits
lui(rd, (int32_t)high_20);
addi(rd, rd, low_12); // 31 bits in rd.
slli(rd, rd, 11); // Space for next 11 bis
ori(rd, rd, b11); // 11 bits are put in. 42 bit in rd
slli(rd, rd, 6); // Space for next 6 bits
ori(rd, rd, a6); // 6 bits are put in. 48 bis in rd
}
void Assembler::li_constant(Register rd, int64_t imm) {